litex/litex/soc/integration
2017-07-19 12:18:35 +02:00
..
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00
builder.py soc/integration/builder: remove error when compile_software=False and integrated ROM: when using compile_software=False user knows what he's doing. 2017-04-26 13:49:16 +02:00
cpu_interface.py soc/integration/cpu_interface: do not generate constant access functions when with_access_functions is set to False 2017-07-19 12:18:35 +02:00
sdram_init.py for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00
soc_core.py soc/core/uart: add UartStub to enable fast simulation with cpu 2017-07-06 19:19:10 +02:00
soc_sdram.py merge most of misoc 54e1ef82 and migen e93d0601 changes 2017-01-13 03:55:00 +01:00