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04c64eb1d8
litex
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misoclib
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com
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liteeth
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example_designs
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Florent Kermarrec
125432b5b6
liteeth/example_designs: use new Keep SynthesisDirective
2015-06-23 16:15:28 +02:00
..
targets
liteeth/example_designs: use new Keep SynthesisDirective
2015-06-23 16:15:28 +02:00
test
use similar names for wishbone bridges and move wishbone drivers to [core]/software
2015-05-02 16:22:30 +02:00
__init__.py
misoclib: better organization (create cores categories: cpu, mem, com, ...)
2015-02-28 09:40:44 +01:00
make.py
lite* cores: changes permissions (+x) on make.py files and on litepcie init.sh file
2015-04-18 08:51:59 -04:00