Florent Kermarrec d73d75007e misoclib/com/uart: cleanup and add irq condition parameters ... - reintroduce RX/TX split (ease comprehension) - use FIFO wrapper function from Migen. - add tx_irq_condition and rx_irq_condition		2015-07-24 12:57:42 +02:00
..
phy	misoclib/com/uart: remove liteeth dependency (copy/paste error)	2015-04-28 18:53:46 +02:00
software	use similar names for wishbone bridges and move wishbone drivers to [core]/software	2015-05-02 16:22:30 +02:00
test	global: more pep8	2015-04-13 18:02:26 +02:00
__init__.py	misoclib/com/uart: cleanup and add irq condition parameters	2015-07-24 12:57:42 +02:00
bridge.py	uart: rename wishbone to bridge	2015-05-09 16:24:28 +02:00