Florent Kermarrec
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d73d75007e
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misoclib/com/uart: cleanup and add irq condition parameters
- reintroduce RX/TX split (ease comprehension)
- use FIFO wrapper function from Migen.
- add tx_irq_condition and rx_irq_condition
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2015-07-24 12:57:42 +02:00 |
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Robert Jordens
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a501d7c52d
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uart: support async phys
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2015-07-19 23:37:00 +02:00 |
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Florent Kermarrec
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a99aa9c7fd
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uart: rename wishbone to bridge
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2015-05-09 16:24:28 +02:00 |
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Florent Kermarrec
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fb5397aa82
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uart: remove litescope dependency for UARTWishboneBridge and remove frontend
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2015-05-09 16:08:20 +02:00 |
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Florent Kermarrec
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3ebe877fd2
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use similar names for wishbone bridges and move wishbone drivers to [core]/software
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2015-05-02 16:22:30 +02:00 |
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Florent Kermarrec
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8aa3fb3eb7
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com/uart: add tx and rx fifos.
Since ressource usage is low with default depth of 16 (implemented in RAM LUTs) we don't keep old behaviour.
Tested successfully with BIOS and flterm.
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2015-05-01 15:59:26 +02:00 |
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Florent Kermarrec
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7fc96da51c
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misoclib/com/uart: remove liteeth dependency (copy/paste error)
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2015-04-28 18:53:46 +02:00 |
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Florent Kermarrec
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2ccb5655c9
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global: more pep8
we will have to continue the work... volunteers are welcome :)
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2015-04-13 18:02:26 +02:00 |
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Florent Kermarrec
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fc68d915c1
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global: pep8 (E261, E271)
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2015-04-13 17:16:12 +02:00 |
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Florent Kermarrec
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01ba965d0c
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global: pep8 (E401)
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2015-04-13 16:56:25 +02:00 |
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Florent Kermarrec
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f68423f423
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global: pep8 (E302)
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2015-04-13 16:47:22 +02:00 |
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Florent Kermarrec
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d9e09707ae
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global: pep8 (replace tabs with spaces)
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2015-04-13 16:19:55 +02:00 |
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Florent Kermarrec
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767d45727a
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uart/liteeth: only import the phy we are going to use (UARTPHYSim cannot be imported on Windows since based on pty).
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2015-03-12 16:57:38 +01:00 |
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Florent Kermarrec
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b157031e8a
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uart/sim: add pty (optional, to use flterm)
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2015-03-09 23:29:06 +01:00 |
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Florent Kermarrec
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d20b9c2221
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uart: pass *args, **kwargs to sim phy
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2015-03-06 12:08:10 +01:00 |
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Florent Kermarrec
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af66ca7bad
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uart: add phy autodetect function
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2015-03-06 10:19:29 +01:00 |
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Florent Kermarrec
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200791c81d
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uart: generate ack for rx (serialboot OK with sim)
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2015-03-04 00:57:37 +01:00 |
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Florent Kermarrec
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f58394f6af
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soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)
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2015-03-01 18:25:47 +01:00 |
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Florent Kermarrec
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096e95cb59
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uart: use data instead of d on endpoint's layouts (coherency with others cores)
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2015-03-01 16:56:48 +01:00 |
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Florent Kermarrec
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1e6d1deae8
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uart: add sim phy
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2015-03-01 16:52:50 +01:00 |
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Florent Kermarrec
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bd4d3cd73b
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uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)
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2015-03-01 12:14:34 +01:00 |
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Florent Kermarrec
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2c51adcd68
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misoclib: better organization (create cores categories: cpu, mem, com, ...)
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2015-02-28 09:40:44 +01:00 |
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