litex/litex
Gabriel Somlo 6fdb36b84a liblitesdcard/sdcard: adjust card-ready timeout
Testing on nexys4ddr and rocket, approximately 12 iterations of the
timeout loop (using `busy_wait(1)`) are needed to receive a "ready"
response from the SDcard, assuming a "warm" reset where the card has
already been previously initialized.

If the SDcard is ejected and re-inserted, or if the board is "cold-reset"
(e.g., reprogrammed via openocd vs. a simple push of the reset button),
it takes approximately 450 iterations before the SDCard responds with a
"ready" message.

In either case, a timeout of 10 is insufficient. This patch increases
the busy-wait to 10, and the timeout loop counter to 128, which should
cover most cases.

Additionally, make a few minor cosmetic improvements.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-07-06 17:38:07 -04:00
..
boards targets: remove sdcard clock domain (now generated in the PHY). 2020-07-03 20:11:05 +02:00
build Improve verilator compilation speed 2020-06-30 10:38:26 +02:00
gen gen/fhdl/verilog: explicitly define input/output/inout wires. 2020-05-05 16:58:33 +02:00
soc liblitesdcard/sdcard: adjust card-ready timeout 2020-07-06 17:38:07 -04:00
tools tools/litex_sim: cleanup cpu endianness. 2020-07-01 09:47:10 +02:00
__init__.py litex/__init__.py: remove retro-compat > 6 months old. 2020-04-30 21:31:58 +02:00