533 lines
18 KiB
Python
533 lines
18 KiB
Python
# This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
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# This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2018 Tim 'mithro' Ansell <me@mith.ro>
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# License: BSD
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from functools import reduce
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from operator import or_
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from migen import *
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from migen.genlib import roundrobin
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from migen.genlib.record import *
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from migen.genlib.misc import split, displacer, chooser, WaitTimer
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from litex.build.generic_platform import *
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from litex.soc.interconnect import csr
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# Wishbone Definition ------------------------------------------------------------------------------
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_layout = [
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("adr", "adr_width", DIR_M_TO_S),
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("dat_w", "data_width", DIR_M_TO_S),
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("dat_r", "data_width", DIR_S_TO_M),
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("sel", "sel_width", DIR_M_TO_S),
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("cyc", 1, DIR_M_TO_S),
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("stb", 1, DIR_M_TO_S),
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("ack", 1, DIR_S_TO_M),
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("we", 1, DIR_M_TO_S),
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("cti", 3, DIR_M_TO_S),
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("bte", 2, DIR_M_TO_S),
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("err", 1, DIR_S_TO_M)
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]
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class Interface(Record):
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def __init__(self, data_width=32, adr_width=30):
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self.data_width = data_width
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self.adr_width = adr_width
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Record.__init__(self, set_layout_parameters(_layout,
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adr_width = adr_width,
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data_width = data_width,
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sel_width = data_width//8))
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self.adr.reset_less = True
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self.dat_w.reset_less = True
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self.dat_r.reset_less = True
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self.sel.reset_less = True
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@staticmethod
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def like(other):
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return Interface(len(other.dat_w))
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def _do_transaction(self):
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yield self.cyc.eq(1)
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yield self.stb.eq(1)
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yield
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while not (yield self.ack):
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yield
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yield self.cyc.eq(0)
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yield self.stb.eq(0)
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def write(self, adr, dat, sel=None):
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if sel is None:
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sel = 2**len(self.sel) - 1
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yield self.adr.eq(adr)
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yield self.dat_w.eq(dat)
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yield self.sel.eq(sel)
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yield self.we.eq(1)
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yield from self._do_transaction()
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def read(self, adr):
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yield self.adr.eq(adr)
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yield self.we.eq(0)
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yield from self._do_transaction()
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return (yield self.dat_r)
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def get_ios(self, bus_name="wb"):
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subsignals = []
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for name, width, direction in self.layout:
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subsignals.append(Subsignal(name, Pins(width)))
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ios = [(bus_name , 0) + tuple(subsignals)]
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return ios
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def connect_to_pads(self, pads, mode="master"):
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assert mode in ["slave", "master"]
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r = []
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for name, width, direction in self.layout:
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sig = getattr(self, name)
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pad = getattr(pads, name)
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if mode == "master":
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if direction == DIR_M_TO_S:
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r.append(pad.eq(sig))
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else:
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r.append(sig.eq(pad))
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else:
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if direction == DIR_S_TO_M:
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r.append(pad.eq(sig))
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else:
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r.append(sig.eq(pad))
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return r
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# Wishbone Timeout ---------------------------------------------------------------------------------
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class Timeout(Module):
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def __init__(self, master, cycles):
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self.error = Signal()
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# # #
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timer = WaitTimer(int(cycles))
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self.submodules += timer
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self.comb += [
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timer.wait.eq(master.stb & master.cyc & ~master.ack),
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If(timer.done,
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master.dat_r.eq((2**len(master.dat_w))-1),
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master.ack.eq(1),
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self.error.eq(1)
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)
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]
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# Wishbone Interconnect ----------------------------------------------------------------------------
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class InterconnectPointToPoint(Module):
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def __init__(self, master, slave):
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self.comb += master.connect(slave)
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class Arbiter(Module):
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def __init__(self, masters, target):
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self.submodules.rr = roundrobin.RoundRobin(len(masters))
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# mux master->slave signals
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for name, size, direction in _layout:
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if direction == DIR_M_TO_S:
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choices = Array(getattr(m, name) for m in masters)
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self.comb += getattr(target, name).eq(choices[self.rr.grant])
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# connect slave->master signals
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for name, size, direction in _layout:
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if direction == DIR_S_TO_M:
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source = getattr(target, name)
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for i, m in enumerate(masters):
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dest = getattr(m, name)
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if name == "ack" or name == "err":
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self.comb += dest.eq(source & (self.rr.grant == i))
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else:
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self.comb += dest.eq(source)
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# connect bus requests to round-robin selector
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reqs = [m.cyc for m in masters]
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self.comb += self.rr.request.eq(Cat(*reqs))
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class Decoder(Module):
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# slaves is a list of pairs:
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# 0) function that takes the address signal and returns a FHDL expression
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# that evaluates to 1 when the slave is selected and 0 otherwise.
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# 1) wishbone.Slave reference.
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# register adds flip-flops after the address comparators. Improves timing,
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# but breaks Wishbone combinatorial feedback.
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def __init__(self, master, slaves, register=False):
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ns = len(slaves)
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slave_sel = Signal(ns)
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slave_sel_r = Signal(ns)
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# decode slave addresses
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self.comb += [slave_sel[i].eq(fun(master.adr))
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for i, (fun, bus) in enumerate(slaves)]
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if register:
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self.sync += slave_sel_r.eq(slave_sel)
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else:
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self.comb += slave_sel_r.eq(slave_sel)
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# connect master->slaves signals except cyc
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for slave in slaves:
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for name, size, direction in _layout:
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if direction == DIR_M_TO_S and name != "cyc":
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self.comb += getattr(slave[1], name).eq(getattr(master, name))
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# combine cyc with slave selection signals
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self.comb += [slave[1].cyc.eq(master.cyc & slave_sel[i])
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for i, slave in enumerate(slaves)]
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# generate master ack (resp. err) by ORing all slave acks (resp. errs)
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self.comb += [
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master.ack.eq(reduce(or_, [slave[1].ack for slave in slaves])),
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master.err.eq(reduce(or_, [slave[1].err for slave in slaves]))
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]
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# mux (1-hot) slave data return
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masked = [Replicate(slave_sel_r[i], len(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
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self.comb += master.dat_r.eq(reduce(or_, masked))
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class InterconnectShared(Module):
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def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
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shared = Interface()
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self.submodules.arbiter = Arbiter(masters, shared)
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self.submodules.decoder = Decoder(shared, slaves, register)
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if timeout_cycles is not None:
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self.submodules.timeout = Timeout(shared, timeout_cycles)
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class Crossbar(Module):
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def __init__(self, masters, slaves, register=False):
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matches, busses = zip(*slaves)
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access = [[Interface() for j in slaves] for i in masters]
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# decode each master into its access row
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for row, master in zip(access, masters):
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row = list(zip(matches, row))
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self.submodules += Decoder(master, row, register)
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# arbitrate each access column onto its slave
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for column, bus in zip(zip(*access), busses):
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self.submodules += Arbiter(column, bus)
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# Wishbone Data Width Converter --------------------------------------------------------------------
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class DownConverter(Module):
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"""DownConverter
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This module splits Wishbone accesses from a master interface to a smaller slave interface.
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Writes:
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Writes from master are splitted N writes to the slave. Access is acked when the last
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access is acked by the slave.
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Reads:
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Read from master are splitted in N reads to the the slave. Read datas from
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the slave are cached before being presented concatenated on the last access.
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"""
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def __init__(self, master, slave):
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dw_from = len(master.dat_r)
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dw_to = len(slave.dat_w)
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ratio = dw_from//dw_to
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# # #
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skip = Signal()
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counter = Signal(max=ratio)
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# Control Path
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fsm = FSM(reset_state="IDLE")
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fsm = ResetInserter()(fsm)
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self.submodules.fsm = fsm
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self.comb += fsm.reset.eq(~master.cyc)
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fsm.act("IDLE",
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NextValue(counter, 0),
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If(master.stb & master.cyc,
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NextState("CONVERT"),
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)
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)
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fsm.act("CONVERT",
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slave.adr.eq(Cat(counter, master.adr)),
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Case(counter, {i: slave.sel.eq(master.sel[i*dw_to//8:]) for i in range(ratio)}),
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If(master.stb & master.cyc,
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skip.eq(slave.sel == 0),
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slave.we.eq(master.we),
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slave.cyc.eq(~skip),
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slave.stb.eq(~skip),
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If(slave.ack | skip,
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NextValue(counter, counter + 1),
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If(counter == (ratio - 1),
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master.ack.eq(1),
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NextState("IDLE")
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)
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)
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)
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)
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# Write Datapath
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self.comb += Case(counter, {i: slave.dat_w.eq(master.dat_w[i*dw_to:]) for i in range(ratio)})
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# Read Datapath
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dat_r = Signal(dw_from, reset_less=True)
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self.comb += master.dat_r.eq(Cat(dat_r[dw_to:], slave.dat_r))
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self.sync += If(slave.ack | skip, dat_r.eq(master.dat_r))
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class Converter(Module):
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"""Converter
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This module is a wrapper for DownConverter and UpConverter.
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It should preferably be used rather than direct instantiations
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of specific converters.
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"""
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def __init__(self, master, slave):
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self.master = master
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self.slave = slave
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# # #
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dw_from = len(master.dat_r)
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dw_to = len(slave.dat_r)
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if dw_from > dw_to:
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downconverter = DownConverter(master, slave)
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self.submodules += downconverter
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elif dw_from < dw_to:
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raise NotImplementedError
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else:
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self.comb += master.connect(slave)
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# Wishbone SRAM ------------------------------------------------------------------------------------
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class SRAM(Module):
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def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
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if bus is None:
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bus = Interface()
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self.bus = bus
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bus_data_width = len(self.bus.dat_r)
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if isinstance(mem_or_size, Memory):
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assert(mem_or_size.width <= bus_data_width)
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self.mem = mem_or_size
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else:
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self.mem = Memory(bus_data_width, mem_or_size//(bus_data_width//8), init=init)
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if read_only is None:
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if hasattr(self.mem, "bus_read_only"):
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read_only = self.mem.bus_read_only
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else:
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read_only = False
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###
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# memory
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port = self.mem.get_port(write_capable=not read_only, we_granularity=8,
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mode=READ_FIRST if read_only else WRITE_FIRST)
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self.specials += self.mem, port
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# generate write enable signal
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if not read_only:
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self.comb += [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
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for i in range(bus_data_width//8)]
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# address and data
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self.comb += [
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port.adr.eq(self.bus.adr[:len(port.adr)]),
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self.bus.dat_r.eq(port.dat_r)
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]
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if not read_only:
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self.comb += port.dat_w.eq(self.bus.dat_w),
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# generate ack
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self.sync += [
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self.bus.ack.eq(0),
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If(self.bus.cyc & self.bus.stb & ~self.bus.ack, self.bus.ack.eq(1))
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]
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# Wishbone To CSR ----------------------------------------------------------------------------------
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class Wishbone2CSR(Module):
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def __init__(self, bus_wishbone=None, bus_csr=None):
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self.csr = bus_csr
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if self.csr is None:
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# If no CSR bus provided, create it with default parameters.
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self.csr = csr_bus.Interface()
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self.wishbone = bus_wishbone
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if self.wishbone is None:
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# If no Wishbone bus provided, create it with default parameters.
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self.wishbone = Interface()
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# # #
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self.comb += [
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self.csr.dat_w.eq(self.wishbone.dat_w),
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self.wishbone.dat_r.eq(self.csr.dat_r)
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]
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fsm = FSM(reset_state="WRITE-READ")
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self.submodules += fsm
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fsm.act("WRITE-READ",
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If(self.wishbone.cyc & self.wishbone.stb,
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self.csr.adr.eq(self.wishbone.adr),
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self.csr.we.eq(self.wishbone.we & (self.wishbone.sel != 0)),
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NextState("ACK")
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)
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)
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fsm.act("ACK",
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self.wishbone.ack.eq(1),
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NextState("WRITE-READ")
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)
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# Wishbone Cache -----------------------------------------------------------------------------------
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class Cache(Module):
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"""Cache
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This module is a write-back wishbone cache that can be used as a L2 cache.
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Cachesize (in 32-bit words) is the size of the data store and must be a power of 2
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"""
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def __init__(self, cachesize, master, slave, reverse=True):
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self.master = master
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self.slave = slave
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# # #
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dw_from = len(master.dat_r)
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dw_to = len(slave.dat_r)
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if dw_to > dw_from and (dw_to % dw_from) != 0:
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raise ValueError("Slave data width must be a multiple of {dw}".format(dw=dw_from))
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if dw_to < dw_from and (dw_from % dw_to) != 0:
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raise ValueError("Master data width must be a multiple of {dw}".format(dw=dw_to))
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# Split address:
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# TAG | LINE NUMBER | LINE OFFSET
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offsetbits = log2_int(max(dw_to//dw_from, 1))
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addressbits = len(slave.adr) + offsetbits
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linebits = log2_int(cachesize) - offsetbits
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tagbits = addressbits - linebits
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wordbits = log2_int(max(dw_from//dw_to, 1))
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adr_offset, adr_line, adr_tag = split(master.adr, offsetbits, linebits, tagbits)
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word = Signal(wordbits) if wordbits else None
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# Data memory
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data_mem = Memory(dw_to*2**wordbits, 2**linebits)
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data_port = data_mem.get_port(write_capable=True, we_granularity=8)
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self.specials += data_mem, data_port
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write_from_slave = Signal()
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if adr_offset is None:
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adr_offset_r = None
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else:
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adr_offset_r = Signal(offsetbits, reset_less=True)
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self.sync += adr_offset_r.eq(adr_offset)
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self.comb += [
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data_port.adr.eq(adr_line),
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If(write_from_slave,
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displacer(slave.dat_r, word, data_port.dat_w),
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displacer(Replicate(1, dw_to//8), word, data_port.we)
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).Else(
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data_port.dat_w.eq(Replicate(master.dat_w, max(dw_to//dw_from, 1))),
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If(master.cyc & master.stb & master.we & master.ack,
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displacer(master.sel, adr_offset, data_port.we, 2**offsetbits, reverse=reverse)
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)
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),
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chooser(data_port.dat_r, word, slave.dat_w),
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slave.sel.eq(2**(dw_to//8)-1),
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chooser(data_port.dat_r, adr_offset_r, master.dat_r, reverse=reverse)
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]
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# Tag memory
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tag_layout = [("tag", tagbits), ("dirty", 1)]
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tag_mem = Memory(layout_len(tag_layout), 2**linebits)
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tag_port = tag_mem.get_port(write_capable=True)
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self.specials += tag_mem, tag_port
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tag_do = Record(tag_layout)
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tag_di = Record(tag_layout)
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self.comb += [
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tag_do.raw_bits().eq(tag_port.dat_r),
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tag_port.dat_w.eq(tag_di.raw_bits())
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]
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self.comb += [
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tag_port.adr.eq(adr_line),
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tag_di.tag.eq(adr_tag)
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]
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if word is not None:
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self.comb += slave.adr.eq(Cat(word, adr_line, tag_do.tag))
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else:
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self.comb += slave.adr.eq(Cat(adr_line, tag_do.tag))
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# slave word computation, word_clr and word_inc will be simplified
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# at synthesis when wordbits=0
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word_clr = Signal()
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word_inc = Signal()
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if word is not None:
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self.sync += \
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If(word_clr,
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word.eq(0),
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).Elif(word_inc,
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word.eq(word+1)
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)
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def word_is_last(word):
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if word is not None:
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return word == 2**wordbits-1
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else:
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return 1
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# Control FSM
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(master.cyc & master.stb,
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NextState("TEST_HIT")
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)
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)
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fsm.act("TEST_HIT",
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word_clr.eq(1),
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If(tag_do.tag == adr_tag,
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master.ack.eq(1),
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If(master.we,
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tag_di.dirty.eq(1),
|
|
tag_port.we.eq(1)
|
|
),
|
|
NextState("IDLE")
|
|
).Else(
|
|
If(tag_do.dirty,
|
|
NextState("EVICT")
|
|
).Else(
|
|
# Write the tag first to set the slave address
|
|
tag_port.we.eq(1),
|
|
word_clr.eq(1),
|
|
NextState("REFILL")
|
|
)
|
|
)
|
|
)
|
|
|
|
fsm.act("EVICT",
|
|
slave.stb.eq(1),
|
|
slave.cyc.eq(1),
|
|
slave.we.eq(1),
|
|
If(slave.ack,
|
|
word_inc.eq(1),
|
|
If(word_is_last(word),
|
|
# Write the tag first to set the slave address
|
|
tag_port.we.eq(1),
|
|
word_clr.eq(1),
|
|
NextState("REFILL")
|
|
)
|
|
)
|
|
)
|
|
fsm.act("REFILL",
|
|
slave.stb.eq(1),
|
|
slave.cyc.eq(1),
|
|
slave.we.eq(0),
|
|
If(slave.ack,
|
|
write_from_slave.eq(1),
|
|
word_inc.eq(1),
|
|
If(word_is_last(word),
|
|
NextState("TEST_HIT"),
|
|
).Else(
|
|
NextState("REFILL")
|
|
)
|
|
)
|
|
)
|