litex/litex/soc/interconnect
Florent Kermarrec f0a97791a9 interconnect/csr_bus: move/rewrite paged access warning.
Was incorrectly triggered with csr_data_width=32.
2020-07-06 12:26:24 +02:00
..
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00
avalon.py add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
axi.py interconnect/axi/AXIStreamInterface: add tuser support. 2020-06-26 08:36:16 +02:00
csr.py interconnect/csr: add reset_less parameter. 2020-04-06 13:15:08 +02:00
csr_bus.py interconnect/csr_bus: move/rewrite paged access warning. 2020-07-06 12:26:24 +02:00
csr_eventmanager.py csr_eventmanager: add `name` and `description` args 2019-09-19 17:23:03 +08:00
packet.py soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty. 2020-01-16 09:46:54 +01:00
stream.py interconnect/stream: allow empty description/payload on Endpoint. 2020-07-03 19:29:05 +02:00
stream_sim.py add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
wishbone.py wishbone/DownConverter: fix read datapath when access is skipped because sel = 0. 2020-06-22 13:37:14 +02:00