Sebastien Bourdeauducq 8e11fcf1d0 bus/csr/SRAM: fix Module conversion errors		2013-04-14 13:55:04 +02:00
..
__init__.py	…
asmibus.py	bus/asmibus: use implicit finalization	2013-03-11 17:11:59 +01:00
csr.py	bus/csr/SRAM: fix Module conversion errors	2013-04-14 13:55:04 +02:00
dfi.py	bus: replace simple bus module with new bidirectional Record	2013-04-01 21:54:21 +02:00
memory.py	sim: remove PureSimulable (superseded by Module)	2013-03-15 19:41:30 +01:00
transactions.py	bus/transactions: add busname parameter	2012-11-17 19:36:08 +01:00
wishbone.py	bus: replace simple bus module with new bidirectional Record	2013-04-01 21:54:21 +02:00
wishbone2asmi.py	bus: replace simple bus module with new bidirectional Record	2013-04-01 21:54:21 +02:00
wishbone2csr.py	corelogic -> genlib	2013-02-22 23:19:37 +01:00