litex/misoclib
Florent Kermarrec 0f9b0c6f0f sdram/module: add MT47H128M8 DDR2 (used for a customer) 2015-03-21 18:52:10 +01:00
..
com litexxx cores: use default baudrate of 115200 for all tests 2015-03-20 12:22:53 +01:00
cpu litescope: create example design derived from SoC that can be used on all targets 2015-02-28 22:19:24 +01:00
mem sdram/module: add MT47H128M8 DDR2 (used for a customer) 2015-03-21 18:52:10 +01:00
others move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future) 2015-02-28 11:51:51 +01:00
soc sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings 2015-03-21 12:55:39 +01:00
tools liteeth: use bios ip_address in example designs 2015-03-18 18:18:43 +01:00
video sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it 2015-03-02 08:36:39 +01:00
__init__.py rename milkymist-ng to MiSoC 2013-11-09 15:27:32 +01:00