Florent Kermarrec 0f9b0c6f0f sdram/module: add MT47H128M8 DDR2 (used for a customer)		2015-03-21 18:52:10 +01:00
..
core	sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings	2015-03-21 12:55:39 +01:00
frontend	sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)	2015-03-02 10:59:43 +01:00
phy	sdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move dfi to phy	2015-03-03 09:55:25 +01:00
test	sdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move dfi to phy	2015-03-03 09:55:25 +01:00
__init__.py	sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings	2015-03-21 12:55:39 +01:00
module.py	sdram/module: add MT47H128M8 DDR2 (used for a customer)	2015-03-21 18:52:10 +01:00