litex/verilog
Michael Walle 10495e72d0 lm32: rename mem array in lm32_dp_ram
Be compatible with original proprietary DP RAM instantiation. This is
needed for simulation, where r0 is initialized to zero in lm32_cpu.v.

Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:08:06 +01:00
..
generic framebuffer: fix FIFO read clocking 2012-07-07 11:30:27 +02:00
lm32 lm32: rename mem array in lm32_dp_ram 2012-11-14 14:08:06 +01:00
m1crg Define clock domains instead of passing extra clocks as regular signals 2012-09-11 00:21:07 +02:00
minimac3 Remove some boilerplate 2012-05-24 19:22:27 +02:00
s6ddrphy asmicon: skeleton 2012-03-14 18:26:05 +01:00