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litex/verilog/lm32
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Michael Walle 10495e72d0 lm32: rename mem array in lm32_dp_ram 
Be compatible with original proprietary DP RAM instantiation. This is
needed for simulation, where r0 is initialized to zero in lm32_cpu.v.

Signed-off-by: Michael Walle <michael@walle.cc>
 		2012-11-14 14:08:06 +01:00
..
jtag_cores.v Initial import 2011-12-13 17:33:12 +01:00
jtag_tap_spartan6.v Initial import 2011-12-13 17:33:12 +01:00
lm32_adder.v Initial import 2011-12-13 17:33:12 +01:00
lm32_addsub.v Initial import 2011-12-13 17:33:12 +01:00
lm32_cpu.v lm32: replace clogb2 by builtin $clog2 2012-11-14 14:07:28 +01:00
lm32_dcache.v lm32: replace clogb2 by builtin $clog2 2012-11-14 14:07:28 +01:00
lm32_debug.v lm32: replace clogb2 by builtin $clog2 2012-11-14 14:07:28 +01:00
lm32_decoder.v lm32: replace clogb2 by builtin $clog2 2012-11-14 14:07:28 +01:00
lm32_dp_ram.v lm32: rename mem array in lm32_dp_ram 2012-11-14 14:08:06 +01:00
lm32_icache.v lm32: replace clogb2 by builtin $clog2 2012-11-14 14:07:28 +01:00
lm32_include.v Initial import 2011-12-13 17:33:12 +01:00
lm32_instruction_unit.v lm32: replace clogb2 by builtin $clog2 2012-11-14 14:07:28 +01:00
lm32_interrupt.v LM32: make IP read-only and interrupt lines level-sensitive 2012-02-07 00:07:12 +01:00
lm32_jtag.v Initial import 2011-12-13 17:33:12 +01:00
lm32_load_store_unit.v lm32: replace clogb2 by builtin $clog2 2012-11-14 14:07:28 +01:00
lm32_logic_op.v Initial import 2011-12-13 17:33:12 +01:00
lm32_mc_arithmetic.v Initial import 2011-12-13 17:33:12 +01:00
lm32_multiplier.v Initial import 2011-12-13 17:33:12 +01:00
lm32_multiplier_spartan6.v Initial import 2011-12-13 17:33:12 +01:00
lm32_ram.v Initial import 2011-12-13 17:33:12 +01:00
lm32_shifter.v Initial import 2011-12-13 17:33:12 +01:00
lm32_top.v lm32: replace clogb2 by builtin $clog2 2012-11-14 14:07:28 +01:00