Florent Kermarrec 8d1c555e36 misoclib/com/uart: remove irq condition parameters and use "non-full" for tx irq, "non-empty" for rx irq. ... An optimal solution for both sync and async mode is not easy to implement, it would requires moving CDC out of UART module and handling in the PHY with AsyncFIFO or minimal depth. For now use the solution that works for both cases. We'll try to optimize that if we have performance issues.		2015-07-25 00:25:09 +02:00
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phy	misoclib/com/uart: remove liteeth dependency (copy/paste error)	2015-04-28 18:53:46 +02:00
software	use similar names for wishbone bridges and move wishbone drivers to [core]/software	2015-05-02 16:22:30 +02:00
test	global: more pep8	2015-04-13 18:02:26 +02:00
__init__.py	misoclib/com/uart: remove irq condition parameters and use "non-full" for tx irq, "non-empty" for rx irq.	2015-07-25 00:25:09 +02:00
bridge.py	uart: rename wishbone to bridge	2015-05-09 16:24:28 +02:00