Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
Build your hardware, easily!
19 Commits 40 Branches 14 Tags 51 MiB
C 52.8%
Python 43.5%
Assembly 1.4%
SystemVerilog 1.3%
Makefile 0.3%
Other 0.6%
Go to file
Sebastien Bourdeauducq 1a4a6eb445 Copy some software code from the original Milkymist SoC. 
Libbase should keep its RAM usage to a minimum as it is meant to
be executed before the SDRAM is up and running. (Having lots of
code is OK though as we XIP from the flash)
 		2012-02-03 12:08:17 +01:00
build Initial import 2011-12-13 17:33:12 +01:00
milkymist sram: fix WE signal 2012-02-03 10:38:17 +01:00
software Copy some software code from the original Milkymist SoC. 2012-02-03 12:08:17 +01:00
tb/norflash Convert -> convert 2012-01-05 19:27:45 +01:00
verilog uart: new design using FHDL and bank (TX only, incomplete) 2011-12-18 00:29:37 +01:00
.gitignore Initial import 2011-12-13 17:33:12 +01:00
build.py Convert -> convert 2012-01-05 19:27:45 +01:00
constraints.py Multiply system clock 2011-12-17 15:00:18 +01:00
top.py Add on-chip SRAM 2012-01-27 22:09:03 +01:00