enjoy-digital 1bb4507d93 Merge pull request #846 from enjoy-digital/axi-lite-downconverter-fix ... interconnect/axi: Fix AXILiteDownverterWrite/Read base address.		2021-03-18 18:15:52 +01:00
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build	build/generic_platform: Minor cosmetic cleanups.	2021-03-10 19:21:02 +01:00
gen	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
soc	Merge pull request #846 from enjoy-digital/axi-lite-downconverter-fix	2021-03-18 18:15:52 +01:00
tools	tools/litex_sim: Add boot to main_ram when sdram_init contents provided.	2021-02-25 09:10:26 +01:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00