litex/misoclib/com
Florent Kermarrec d9b15e6ef6 cores: replace Timeout with new WaitTimer 2015-05-12 16:14:38 +02:00
..
liteeth cores: replace Timeout with new WaitTimer 2015-05-12 16:14:38 +02:00
litepcie uart: rename wishbone to bridge 2015-05-09 16:24:28 +02:00
liteusb cores: replace Timeout with new WaitTimer 2015-05-12 16:14:38 +02:00
spi global: pep8 (W262) 2015-04-13 17:02:59 +02:00
uart uart: rename wishbone to bridge 2015-05-09 16:24:28 +02:00
__init__.py misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00
gpio.py cores: avoid having too much directories when possible (for simple cores or cores contained in a single file) 2015-05-02 16:22:33 +02:00