Florent Kermarrec 67159349d6 soc/interconnect: remove axi_lite ... axi_lite code was defining AXI4Lite signals and doing a AXI4Lite bridge to the CSR bus when LiteX was not having proper AXI support. LiteX now has proper AXI support and it also cover what axi_lite was doing: To create a AXILite to CSR bus, user can create an AXILite2Wishbone bridge and then connect the CSR bus directly to the wishbone bus as done in the others non-AXI SoC.		2019-05-11 09:12:20 +02:00
..
__init__.py	add test directory with test_code_8b10b.py (from misoc)	2017-04-24 18:46:55 +02:00
test_axi.py	soc/interconnect/axi: add burst support to AXI2Wishbone	2019-04-29 16:49:20 +02:00
test_code_8b10b.py	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00
test_csr.py	test: add basic test_csr	2019-02-27 21:46:00 +01:00
test_gearbox.py	test: remove waveforms generation	2019-04-22 08:41:28 +02:00
test_targets.py	boards: add initial NeTV2 support (clocks, leds, dram, ethernet)	2019-05-10 18:55:40 +02:00