Florent Kermarrec 1fd189512f liteusb/frontend/dma: remove +4 to length for CRC (we'll do it in core)		2015-05-08 23:10:08 +02:00
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__init__.py	liteusb: add simple example design with wishbone bridge and software to control it	2015-05-02 18:21:18 +02:00
dma.py	liteusb/frontend/dma: remove +4 to length for CRC (we'll do it in core)	2015-05-08 23:10:08 +02:00
uart.py	liteusb: continue refactoring (virtual UART and DMA working on minispartan6)	2015-05-01 16:11:15 +02:00
wishbone.py	liteusb/frontend/wishbone: use new packetized mode (allow grouping response in a single packet)	2015-05-02 16:22:45 +02:00