Florent Kermarrec 1fd189512f liteusb/frontend/dma: remove +4 to length for CRC (we'll do it in core)		2015-05-08 23:10:08 +02:00
..
liteeth	liteeth/core/mac: minor cleanup	2015-05-02 16:48:57 +02:00
litepcie	rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq)	2015-05-02 17:07:58 +02:00
liteusb	liteusb/frontend/dma: remove +4 to length for CRC (we'll do it in core)	2015-05-08 23:10:08 +02:00
spi	global: pep8 (W262)	2015-04-13 17:02:59 +02:00
uart	use similar names for wishbone bridges and move wishbone drivers to [core]/software	2015-05-02 16:22:30 +02:00
__init__.py	misoclib: better organization (create cores categories: cpu, mem, com, ...)	2015-02-28 09:40:44 +01:00
gpio.py	cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)	2015-05-02 16:22:33 +02:00