litex/litex
2024-09-26 18:06:36 +02:00
..
build build/efinix/efinity: Cosmetic cleanup on toolchain arguments. 2024-09-26 18:06:36 +02:00
compat compat/soc_core: Fix register_mem/rom missing imports. 2022-11-09 19:11:15 +01:00
gen gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog. 2024-07-03 21:44:31 +02:00
soc soc/cores/vexriscv_smp: Add the generation of the default sim config (https://github.com/litex-hub/linux-on-litex-vexriscv/issues/405) 2024-09-25 10:38:37 +02:00
tools Merge pull request from motec-research/dts_zephyr_updates 2024-09-17 14:58:51 +02:00
__init__.py get_data_mod(): fix recursive exception reporting 2024-04-22 12:09:45 +10:00