Robert Jordens bd232f3f61 fhdl.structure: do not permit clock domain names that start with numbers		2014-08-18 11:01:56 +08:00
..
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
bitcontainer.py	migen/fhdl/bitcontainer: fix signed arrays (map is an iterator)	2013-12-10 23:32:12 +01:00
decorators.py	replace use of __dict__ with dir()/xdir()	2013-11-02 16:03:47 +01:00
edif.py	fhdl/edif: adjust for use with mibuild	2013-08-03 10:54:06 +02:00
module.py	Add 'passive' simulation functions that are not taken into account while determining when to stop the simulator	2014-01-27 23:58:46 +01:00
namer.py	replace use of __dict__ with dir()/xdir()	2013-11-02 16:03:47 +01:00
simplify.py	fhdl/simplify/FullMemoryWE: fix WE slice for multi-port mems	2013-12-13 00:02:50 +01:00
specials.py	specials/Memory: allow for more flexibility in memory port signals	2013-12-12 17:36:17 +01:00
std.py	fhdl.size: rename to bitcontainer	2013-12-03 22:51:52 +01:00
structure.py	fhdl.structure: do not permit clock domain names that start with numbers	2014-08-18 11:01:56 +08:00
tools.py	migen/fhdl/tools: speed up group_by_targets (halves the mixxeo runtime)	2013-12-17 18:40:49 +01:00
tracer.py	bank: automatic register naming	2013-03-12 15:45:24 +01:00
verilog.py	fhdl/verilog: fix representation of negative integers	2013-12-11 22:26:10 +01:00
visit.py	fhdl: do not export Fragment	2013-07-25 18:52:54 +02:00