Tim 'mithro' Ansell 22d454efcd Hack to fix #136.		2018-12-16 14:40:10 -08:00
..
cores	soc/cores/cpu/vexriscv: add add_debug method for debug variants	2018-12-12 10:01:49 +01:00
integration	soc/integration/soc_core: add csr_map_update function	2018-11-21 08:39:52 +01:00
interconnect	soc/interconnect/stream: add support for buffered async fifo	2018-12-08 01:24:08 +01:00
software	Hack to fix #136.	2018-12-16 14:40:10 -08:00
tools	create utils directory and move the litex utils to it	2018-11-16 14:37:19 +01:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
MISOC_LICENSE	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00