Florent Kermarrec 23c33cfa99 build: automatically add keep attribute to signals with timing constraints. ... Avoid having to specify it manually or eventually forget to do it and have a constraints that is not applied correctly.		2019-12-06 15:41:15 +01:00
..
boards	targets/nexys4ddr: remove MEMTEST_ADDR_SIZE limitation (no longer needed)	2019-12-03 10:11:15 +01:00
build	build: automatically add keep attribute to signals with timing constraints.	2019-12-06 15:41:15 +01:00
gen	gen/fhdl/verilog: allow single element verilog inline attribute	2019-08-28 05:24:11 +02:00
soc	soc/interconnect/csr: add fields support for CSRStorage's write simulation method	2019-12-02 09:44:44 +01:00
tools	tools/remote/comm_udp: only use one socket	2019-11-22 15:28:35 +01:00
__init__.py	soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)	2019-09-30 23:41:07 +02:00