Sebastien Bourdeauducq 261166d92b fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style) ... See http://jandecaluwe.com/hdldesign/counting.html		2012-11-29 22:59:54 +01:00
..
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
autofragment.py	Pay a bit more attention to PEP8	2011-12-16 16:02:55 +01:00
namer.py	fhdl/namer: better handling of indices	2012-09-09 19:33:55 +02:00
structure.py	fhdl/structure: add unary minus	2012-11-29 22:52:57 +01:00
tools.py	New specification for width and signedness	2012-11-29 21:22:38 +01:00
tracer.py	fhdl/namer: better handling of indices	2012-09-09 19:33:55 +02:00
verilog.py	fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)	2012-11-29 22:59:54 +01:00
verilog_mem_behavioral.py	Multi-clock design support + new instance API	2012-09-10 23:45:02 +02:00
visit.py	Refactor Case	2012-11-29 01:11:15 +01:00