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litex/misoclib/mem/litesata/example_designs
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Florent Kermarrec 52f1c45407 LiteXXX cores: fix test_reg.py 2015-03-04 23:13:14 +01:00
..
build litesata: fix permissions and imports 2015-03-04 00:46:24 +00:00
platforms litesata: fix permissions and imports 2015-03-04 00:46:24 +00:00
targets liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen 2015-03-01 16:48:41 +01:00
test LiteXXX cores: fix test_reg.py 2015-03-04 23:13:14 +01:00
make.py litesata: fix permissions and imports 2015-03-04 00:46:24 +00:00