Sebastien Bourdeauducq 29b468529f bus: replace simple bus module with new bidirectional Record		2013-04-01 21:54:21 +02:00
..
actorlib	New CSR API	2013-03-30 17:28:41 +01:00
bank	New CSR API	2013-03-30 17:28:41 +01:00
bus	bus: replace simple bus module with new bidirectional Record	2013-04-01 21:54:21 +02:00
fhdl	fhdl/module/finalize: pass additional args to do_finalize	2013-03-30 11:29:46 +01:00
flow	New CSR API	2013-03-30 17:28:41 +01:00
genlib	New bidirectional-capable Record API	2013-04-01 21:53:33 +02:00
pytholite	Use common definition for FinalizeError	2013-03-09 19:03:13 +01:00
sim	sim: remove PureSimulable (superseded by Module)	2013-03-15 19:41:30 +01:00
uio	uio/ioo: fix specials	2013-02-25 23:13:38 +01:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00