litex/litex
Florent Kermarrec 2a91deadcb soc/cores/clock/iCE40PLL: add SB_PLL40_PAD support. 2020-03-09 19:03:05 +01:00
..
boards targets/icebreaker: simplify, use standard VexRiscv, add iCE40PLL and run BIOS from SPI Flash. 2020-03-09 19:01:16 +01:00
build build/lattice/icestorm: add timingstrict parameter and default to False. (similar behavior than others backends) 2020-03-09 19:02:23 +01:00
gen gen/fhdl/verilog: fix signed init values 2020-01-12 22:06:35 +01:00
soc soc/cores/clock/iCE40PLL: add SB_PLL40_PAD support. 2020-03-09 19:03:05 +01:00
tools Fix copyrights 2020-03-05 17:44:10 +01:00
__init__.py soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) 2019-09-30 23:41:07 +02:00