litex/litex
Gabriel Somlo 2c39304110 software, integration/export: rename and reimplement CSR accessors
Implement CSR accessors for all standard integer types and
combinations of subregister alignments (32 or 64 bit) and
sizes (i.e., csr_data_width 8, 16, or 32).

Rename accessors to better reflect the size of the register
being accessed, and correspondingly update the generation
of "csr.h" in "export.py".

Additionally, provide read/write accessors that superimpose arrays
of standard unsigned C types over a CSR register (which may itself
be spread across multiple subregisters).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-01-13 10:09:02 -05:00
..
boards SoCCore: set integrated rom/sram size default values in soc_core_args and use it in targets 2020-01-13 15:03:36 +01:00
build Add optional 'ignore-loops' flag to nextpnr 2020-01-10 16:07:56 +01:00
gen gen/fhdl/verilog: fix signed init values 2020-01-12 22:06:35 +01:00
soc software, integration/export: rename and reimplement CSR accessors 2020-01-13 10:09:02 -05:00
tools tools/remote/comm_udp: only use one socket 2019-11-22 15:28:35 +01:00
__init__.py soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) 2019-09-30 23:41:07 +02:00