Florent Kermarrec 2d23ab7a85 soc/sdram: fix do_finalize		2015-04-01 22:38:04 +02:00
..
com	liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBXXX, move PHY outside of core (builds on minispartan6)	2015-03-22 11:11:37 +01:00
cpu	soc: remove cpu_or_bridge and with_cpu arguments	2015-04-01 17:29:51 +08:00
mem	litesata: adapt to new SoC API	2015-04-01 17:37:53 +08:00
others	move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future)	2015-02-28 11:51:51 +01:00
soc	soc/sdram: fix do_finalize	2015-04-01 22:38:04 +02:00
tools	liteeth: use bios ip_address in example designs	2015-03-18 18:18:43 +01:00
video	sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it	2015-03-02 08:36:39 +01:00
__init__.py	…