Fin Maaß 2d96e99494 build: io: SDRTristate: move check ... check wraped signals instead of before. Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>		2024-10-23 11:18:57 +02:00
..
build	build: io: SDRTristate: move check	2024-10-23 11:18:57 +02:00
compat	compat/soc_core: Fix register_mem/rom missing imports.	2022-11-09 19:11:15 +01:00
gen	gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.	2024-07-03 21:44:31 +02:00
soc	soc/integration/soc: Cleanup imports and directly use math.log2/ceil since math is already imported.	2024-10-02 17:10:08 +02:00
tools	Merge pull request #1974 from motec-research/dts_zephyr_updates	2024-09-17 14:58:51 +02:00
__init__.py	get_data_mod(): fix recursive exception reporting	2024-04-22 12:09:45 +10:00