Florent Kermarrec 649cdeb265 liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen		2015-03-01 16:48:41 +01:00
..
targets	liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen	2015-03-01 16:48:41 +01:00
test	liteXXX cores: share same methodology for on-board tests	2015-03-01 11:21:12 +01:00
__init__.py	misoclib: better organization (create cores categories: cpu, mem, com, ...)	2015-02-28 09:40:44 +01:00
make.py	liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins	2015-02-28 23:33:00 +01:00