Matthias Breithaupt 2fd8c2cd61 sim: add HW_PREAMBLE_CRC for ethernet ... This fixes the behavior of `ethernet_phy_model` `"sim"`. As the preamble is automatically attached by the tap, there is no need to add it from the BIOS. To let the BIOS know, `HW_PREAMBLE_CRC` needs to be set. Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>		2024-09-12 10:07:43 +02:00
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build	soc/cores/clock/efinix.py: fill platform.clks with clkout mapping cd/clk_out_name. litex/build/efinix/ifacewriter.py: generate_lvds: when slow_clk/fast_clk are ClockSignal uses platform.clks to map between domain and signal name	2024-09-10 18:07:34 +02:00
compat	compat/soc_core: Fix register_mem/rom missing imports.	2022-11-09 19:11:15 +01:00
gen	gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.	2024-07-03 21:44:31 +02:00
soc	Merge pull request #2060 from Dolu1990/efinix-rework	2024-09-10 18:40:10 +02:00
tools	sim: add HW_PREAMBLE_CRC for ethernet	2024-09-12 10:07:43 +02:00
__init__.py	get_data_mod(): fix recursive exception reporting	2024-04-22 12:09:45 +10:00