David Shah 321dd8fcf6 versa_ecp5: Remove negative diff IO pins ... In Lattice FPGAs only the positive side of differential pairs should be specified (unlike Xilinx) These are a warning on Diamond (which trims unused IO) and an error with Yosys/nextpnr (which doesn't so they conflict when the positive pin is 'expanded'). Already this is the case for the clock input, this commit performs the same change for the DDR3 pins.		2019-02-22 12:12:10 +00:00
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boards	versa_ecp5: Remove negative diff IO pins	2019-02-22 12:12:10 +00:00
build	build/lattice/common/LatticeECXTrellisImpl: add support for nbits == 1	2019-02-11 19:41:12 +01:00
gen	gen/sim/core: add args support on Display	2018-12-09 09:46:10 +01:00
soc	soc/tools/remote/comm_uart: be sure to flush in waiting bytes before read and write	2019-02-16 00:08:24 +01:00
utils	utils/litex_server: allow specify uart_baudrate as float	2019-01-03 10:38:14 +01:00
__init__.py	ease RemoteClient import	2018-09-23 10:23:00 +02:00