Florent Kermarrec 334ae336bf soc/integration: rename cpu_interface to export (with retro-compat), re-arrange a bit, add separators		2019-09-29 17:23:26 +02:00
..
boards	targets/ulx3s: revert to cl=2	2019-09-25 14:09:44 +02:00
build	build/xilinx/programmer: fix vivado_cmd	2019-09-24 14:40:48 +02:00
gen	gen/fhdl/verilog: allow single element verilog inline attribute	2019-08-28 05:24:11 +02:00
soc	soc/integration: rename cpu_interface to export (with retro-compat), re-arrange a bit, add separators	2019-09-29 17:23:26 +02:00
tools	tools/litex_read_verilog: also delete yosys_v2j.ys	2019-09-24 08:49:00 +02:00
__init__.py	tools: move from litex.soc.tools to litex.tools and fix usb.core import	2019-04-20 10:44:53 +02:00