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Sebastien Bourdeauducq 33da32417a Update gitignore 2012-02-05 20:01:14 +01:00
build Initial import 2011-12-13 17:33:12 +01:00
milkymist sram: fix WE signal 2012-02-03 10:38:17 +01:00
software flash: remove splash screens 2012-02-05 19:12:33 +01:00
tb/norflash Convert -> convert 2012-01-05 19:27:45 +01:00
tools Add tools 2012-02-05 19:14:24 +01:00
verilog uart: new design using FHDL and bank (TX only, incomplete) 2011-12-18 00:29:37 +01:00
.gitignore Update gitignore 2012-02-05 20:01:14 +01:00
build.py Convert -> convert 2012-01-05 19:27:45 +01:00
constraints.py Multiply system clock 2011-12-17 15:00:18 +01:00
top.py Memory map 2012-02-05 19:54:08 +01:00