Marcus Comstedt 6da1482336 gen/fhdl/verilog: Fix #1777.		2023-09-14 17:53:51 +02:00
..
build	build/efinix/common: Add EfinixClkInput/Ouptut to use then in RGMII PHYs and avoid duplicating block code.	2023-09-12 09:30:45 +02:00
compat	compat/soc_core: Fix register_mem/rom missing imports.	2022-11-09 19:11:15 +01:00
gen	gen/fhdl/verilog: Fix #1777.	2023-09-14 17:53:51 +02:00
soc	core/vexriscv_smp add --expose-time, which add "clint_time" as output of the cpu.	2023-09-12 10:42:44 +02:00
tools	tools/litex_client: Add binary mode to read_memory and fix hex/binary prefix in dump_registers.	2023-09-08 16:12:04 +02:00
__init__.py	colorer: Avoid duplication and move it to litex/gen.	2022-11-03 09:49:51 +01:00