litex/misoclib/mem
Florent Kermarrec 3b9f287bab sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon 2015-06-17 15:30:30 +02:00
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flash spiflash: fix miso bitbang with large DQ 2015-05-06 00:05:25 +08:00
litesata litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :) 2015-06-10 12:15:59 +02:00
sdram sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon 2015-06-17 15:30:30 +02:00
__init__.py misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00