litex/mibuild
Sebastien Bourdeauducq 38e92eb92b altera_quartus: fix clock domain name 2013-03-26 23:05:46 +01:00
..
platforms altera_quartus, de0nano: add copyright notices 2013-03-15 12:37:25 +01:00
__init__.py Initial version 2013-02-07 22:07:30 +01:00
altera_quartus.py altera_quartus: fix clock domain name 2013-03-26 23:05:46 +01:00
crg.py New clock_domain API 2013-03-15 18:46:11 +01:00
generic_platform.py Support for platform info 2013-03-26 19:17:35 +01:00
tools.py Support adding Verilog/VHDL files 2013-02-08 20:25:20 +01:00
xilinx_ise.py Support for platform info 2013-03-26 19:17:35 +01:00