Robert Jordens 14b1da4018 test_actor: add unittests for SimActor ... * also implicitly tests for the access of signals during simulation that are not referenced in any statements * before, if the busy signal is never used, it is stripped and could not be accessed in simulation		2015-03-21 10:02:10 +01:00
..
actorlib
bank
bus
fhdl	fhdl/verilog: fix dummy signal initial event	2015-03-19 00:24:30 +01:00
flow
genlib	migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb)	2015-03-18 14:41:43 +01:00
sim	sim: keep track of unreferenced items	2015-03-21 10:02:10 +01:00
test	test_actor: add unittests for SimActor	2015-03-21 10:02:10 +01:00
util
__init__.py