Andrew Dennison 3a890a077b software/liblitespi/spiflash: fix clk_freq tuning with L2 cache ... Correct CRC was always calculated, regardless of divisor, as the test flash block was in the L2 cache. This resulted in the minimum divisor being used and incorrect flash reads with 200MHz sys_clock.		2024-02-01 14:37:22 +11:00
..
build	build/openfpgaloader: report command line on error	2024-02-01 14:37:16 +11:00
compat
gen	sim/gtkwave: Update/fix SignalNamespace import (And make it public in fhdl/namer).	2023-11-09 10:29:43 +01:00
soc	software/liblitespi/spiflash: fix clk_freq tuning with L2 cache	2024-02-01 14:37:22 +11:00
tools	tools/litex_server.py: jtag/udp mode: add missing addr_width parameter	2023-12-09 06:08:53 +01:00
__init__.py