litex/migen
Robert Jordens 4091af69fd fhdl/decorators: make the transform logic more idiomatic
* the transformers work on classes and instances.
  you can now do just do:

    @ResetInserter()
    @ClockDomainRenamer({"sys": "new"})
    class Foo(Module):
        pass

  or:

    a = ResetInserter()(FooModule())

* the old usage semantics still work
* the old DecorateModule is deprecated,
  ModuleDecorator has been refactored into ModuleTransformer
  (because it not only decorates things)
2015-04-04 19:16:50 +08:00
..
actorlib remove use of _r prefix on CSRs 2015-04-02 12:15:56 +02:00
bank migen/bank/description: remove support of _r prefix in CSRs 2015-04-02 12:13:22 +02:00
bus move dfi/lasmibus/wishbone2lasmi to MiSoC sdram 2015-02-27 16:54:22 +01:00
fhdl fhdl/decorators: make the transform logic more idiomatic 2015-04-04 19:16:50 +08:00
flow remove use of _r prefix on CSRs 2015-04-02 12:15:56 +02:00
genlib migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb) 2015-03-18 14:41:43 +01:00
sim Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions" 2015-03-30 19:41:16 +08:00
test test_actor: add unittests for SimActor 2015-03-21 10:02:10 +01:00
util utils/misc: add gcd_multiple function to compute GCD or any number of integers 2013-12-12 17:36:50 +01:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00