Matthias Breithaupt 41b346d141 bios: mem_read: reduce number of reads on mapped registers (only supports 32-bit aligned addresses) ... Instead of reading each individual byte, causing multiple 4-byte requests to each address, this change results in a single read for each address. Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>		2024-08-01 15:51:45 +02:00
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build	build/altera/common.py: implement SDRTristate for Agilex5 family	2024-07-30 16:36:05 +02:00
compat	compat/soc_core: Fix register_mem/rom missing imports.	2022-11-09 19:11:15 +01:00
gen	gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.	2024-07-03 21:44:31 +02:00
soc	bios: mem_read: reduce number of reads on mapped registers (only supports 32-bit aligned addresses)	2024-08-01 15:51:45 +02:00
tools	tools/litex_sim: Cleanup imports.	2024-07-18 12:16:23 +02:00
__init__.py	get_data_mod(): fix recursive exception reporting	2024-04-22 12:09:45 +10:00