litex

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Tim 'mithro' Ansell 44650dffd8 cpu: Adding "variant" support. It is useful to support slightly different variants of the CPU configurations. This adds a "cpu_variant" option. For the mor1k we now have the default mor1k configuration and the "linux" variant which enables the features needed for Linux support on the mor1k. Currently there are no variants for the lm32, but we will likely add a "tiny" variant for usage on the iCE40.		2017-12-30 01:18:51 +01:00
doc	doc: update logo	2015-11-13 23:40:27 +01:00
litex	cpu: Adding "variant" support.	2017-12-30 01:18:51 +01:00
test	test/test_gearbox: continue, but we are hitting a simulator bug (related to clock domains declared in modules)	2017-04-25 10:57:34 +02:00
.gitignore	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
.gitmodules	litex/build/sim: add tapcfg submodule for ethernet	2017-06-28 16:18:15 +02:00
LICENSE	add LICENSE, update copyrights, add Migen install instructions	2015-11-11 13:22:39 +01:00
MANIFEST.in	initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush)	2016-04-01 00:09:17 +02:00
README	Fix typo in README: experimental	2017-11-08 21:42:07 -05:00
setup.py	add test directory with test_code_8b10b.py (from misoc)	2017-04-24 18:46:55 +02:00

README

                       __   _ __      _  __
                      / /  (_) /____ | |/_/
                     / /__/ / __/ -_)>  <
                    /____/_/\__/\__/_/|_|
                         Migen inside

                Build your hardware, easily!
             Copyright 2012-2017 Enjoy-Digital

[> Intro
--------
LiteX is an alternative to Migen/MiSoC maintained and used by Enjoy-Digital
to build our cores, integrate them in complete SoC and load/flash them to
the hardware and experiment new features.

The structure of LiteX is kept close to Migen/MiSoC to ease collaboration
between projects and efforts are made to keep cores developed with LiteX
compatible with Migen/MiSoC.

[> License
----------
LiteX is Copyright (c) 2012-2017 Enjoy-Digital under BSD Lisense.
Since it is based on Migen/MiSoC, please also refer to LICENSE file in gen/soc
directory or git history to get correct copyrights.

[> Sub-packages
---------------
gen:
  Provides specific or experimental modules to generate HDL that are not integrated
  in Migen.

build:
  Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to
  simulate HDL code or full SoCs.

soc:
  Provides definitions/modules to build cores (bus, bank, flow), cores and tools
  to build a SoC from such cores.

boards:
  Provides platforms and targets for the supported boards.

[> Quick start guide
--------------------
0. If cloned from Git without the --recursive option, get the submodules:
  git submodule update --init

1. Install Python 3.3+ and FPGA vendor's development tools and JTAG tools.

2. Compile and install binutils. Take the latest version from GNU.
  mkdir build && cd build
  ../configure --target=lm32-elf
  make
  make install

3. (Optional, only if you want to use a lm32 CPU in you SoC)
  Compile and install GCC. Take gcc-core and gcc-g++ from GNU
  (version 4.5 or >=4.9).
  rm -rf libstdc++-v3
  mkdir build && cd build
  ../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc \
    --disable-libssp
  make
  make install

4. Build the target of your board...:
  Go to boards/targets and execute the target you want to build

5. ... and/or install Verilator and test LiteX on your computer:
  Download and install Verilator: http://www.veripool.org/
  Install libevent-devel / json-c-devel packages
  Go to boards/targets
  ./sim.py

6. Run a terminal program on the board's serial port at 115200 8-N-1.
  You should get the BIOS prompt.

[> Contact
----------
E-mail: florent [AT] enjoy-digital.fr