Florent Kermarrec 458e0057f2 soc/interconnect/wishbone: Add Bypass mode on Cache when cachesize == 0 and similar data_widths.		2024-09-09 18:24:14 +02:00
..
build	build/efinix/platform: fix get_pin_name()	2024-09-04 14:42:45 +02:00
compat	compat/soc_core: Fix register_mem/rom missing imports.	2022-11-09 19:11:15 +01:00
gen	gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.	2024-07-03 21:44:31 +02:00
soc	soc/interconnect/wishbone: Add Bypass mode on Cache when cachesize == 0 and similar data_widths.	2024-09-09 18:24:14 +02:00
tools	json2dts_zephyr: omit disable handler	2024-08-20 11:23:21 +02:00
__init__.py	get_data_mod(): fix recursive exception reporting	2024-04-22 12:09:45 +10:00