Florent Kermarrec 4648db0c2a cores/uart/UARTInterface: remove connect method		2020-01-13 16:58:00 +01:00
..
boards	SoCCore: set integrated rom/sram size default values in soc_core_args and use it in targets	2020-01-13 15:03:36 +01:00
build	Add optional 'ignore-loops' flag to nextpnr	2020-01-10 16:07:56 +01:00
gen	gen/fhdl/verilog: fix signed init values	2020-01-12 22:06:35 +01:00
soc	cores/uart/UARTInterface: remove connect method	2020-01-13 16:58:00 +01:00
tools
__init__.py