Florent Kermarrec 571ce5791a litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization ... self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.		2015-06-10 12:14:48 +02:00
..
com	liteusb/core/packet: fix missing ,	2015-05-25 13:53:02 +02:00
cpu	misoclib/cpu: merge git.py in identifier	2015-05-02 18:42:33 +02:00
mem	litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization	2015-06-10 12:14:48 +02:00
others	cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)	2015-05-02 16:22:33 +02:00
soc	sdram: use new Migen Converter in Minicon frontend and small cleanup	2015-06-02 19:37:08 +02:00
tools	cores: replace Timeout with new WaitTimer	2015-05-12 16:14:38 +02:00
video	global: more pep8	2015-04-13 18:02:26 +02:00
__init__.py	rename milkymist-ng to MiSoC	2013-11-09 15:27:32 +01:00