Florent Kermarrec 571ce5791a litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization ... self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.		2015-06-10 12:14:48 +02:00
..
flash	spiflash: fix miso bitbang with large DQ	2015-05-06 00:05:25 +08:00
litesata	litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization	2015-06-10 12:14:48 +02:00
sdram	sdram: use new Migen Converter in Minicon frontend and small cleanup	2015-06-02 19:37:08 +02:00
__init__.py	misoclib: better organization (create cores categories: cpu, mem, com, ...)	2015-02-28 09:40:44 +01:00