litex/litex/soc
2020-03-21 19:54:36 +01:00
..
cores soc/core/spi: add Clk Divider CSR (defaults to sys_clk_freq/spi_clk_freq). 2020-03-20 19:49:42 +01:00
doc Don't let python convert lane number to float. 2020-03-19 18:12:41 -07:00
integration integration/soc: add add_etherbone method. 2020-03-21 19:54:36 +01:00
interconnect Fix copyrights 2020-03-05 17:44:10 +01:00
software Reclock spi sdcard access after initialisation 2020-03-21 07:37:21 +00:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00