Karol Gugala da580e31fd Fix copyrights ... Signed-off-by: Karol Gugala <kgugala@antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>		2020-03-05 17:44:10 +01:00
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__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
avalon.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
axi.py	Fix copyrights	2020-03-05 17:44:10 +01:00
csr.py	soc/interconnect/csr: add fields support for CSRStorage's write simulation method	2019-12-02 09:44:44 +01:00
csr_bus.py	soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment)	2020-02-18 09:13:32 +01:00
csr_eventmanager.py	csr_eventmanager: add name and description args	2019-09-19 17:23:03 +08:00
packet.py	soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty.	2020-01-16 09:46:54 +01:00
stream.py	interconnect/stream/SyncFIFO: allow depth down to 0.	2020-02-28 21:54:02 +01:00
stream_sim.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
wishbone.py	litex_gen/wishbone: simplify the way the bus is exposed as ios and connected to pads.	2020-02-24 12:48:20 +01:00
wishbone2csr.py	wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal)	2019-09-24 17:55:29 +02:00
wishbonebridge.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00