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https://github.com/enjoy-digital/litex.git
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5c939b85ef
litex
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misoclib
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com
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Florent Kermarrec
5c939b85ef
liteeth/core/arp: fix table timer (wait_timer adaptation issue)
2015-06-23 00:25:26 +02:00
..
liteeth
liteeth/core/arp: fix table timer (wait_timer adaptation issue)
2015-06-23 00:25:26 +02:00
litepcie
uart: rename wishbone to bridge
2015-05-09 16:24:28 +02:00
liteusb
liteusb/core/packet: fix missing ,
2015-05-25 13:53:02 +02:00
spi
global: pep8 (W262)
2015-04-13 17:02:59 +02:00
uart
uart: rename wishbone to bridge
2015-05-09 16:24:28 +02:00
__init__.py
misoclib: better organization (create cores categories: cpu, mem, com, ...)
2015-02-28 09:40:44 +01:00
gpio.py
cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)
2015-05-02 16:22:33 +02:00